1. Technical Field
The present invention relates generally to micro-architecture design of digital data processors and, more particularly, to an apparatus for controlling a multibank stack storage device embedded in a digital data processor.
2. Description of Related Art
Many conventional programmable digital data processors, such as microcontroller units (MCUs) and digital signal processors (DSPs), use stack-based instruction sets. A data stack is a storage device that stores information in such a manner that the last stored information item is the first item retrieved, i.e., a stack is accessed in a Last-In, First-Out (LIFO) fashion.
In general, two operations of a stack are the insertion and deletion of stack items. When a new item is inserted to the stack, it is said to be “pushed” onto the stack. Conversely, when an item is deleted from the stack, it is said to be “popped” off the stack. The stack may store program data such as operands or their results, or address pointers, subroutine parameters, and register contents for either subroutine calls and returns or interrupt acknowledges and returns. All “push” and “pop” operations are performed by utilizing the top of the stack. In other words, the top of stack (TOS) is the memory location that is normally read or written. The register that holds the address for the stack is called a stack pointer (SP). This pointer indicates the location of the top of the stack.
In a system (e.g., a computer) having a digital data processor chip, a stack may exist as a stand-alone unit or may be implemented in a random access memory (RAM) unit attached to the processor chip. This stack is organized from a software point of view, and is generally called a “software” stack (sometimes called a “memory” stack). Also, a stack can be organized as a collection of a finite number of registers embedded within a digital processor chip. This type of stack is called a “hardware” stack (sometimes called a “register stack”).
The software stack is convenient to use because it allows a user to adjust the stack to a desired size. But, its structure is disadvantageous in view of operating speed and power dissipation since it is required to access external units. On the other hand, the embedded hardware stack structure is suitable for meeting the higher stack operation requirements, for example, a context switching (in which all the contents of several internal registers of the processor chip are saved on the stack for a short time). Also, the hardware stack requires low power consumption because there is no need for accessing any external unit such as a memory. Consequently, such stack-embedded processors have been used for small battery-powered systems having low power consumption requirements, such as mobile telephones. The drawback of the embedded stack is that users cannot change its size.
FIG. 1 shows the organization of a conventional hardware stack. Referring to FIG. 1, the stack 10 has the storage capacity of 32 words. The stack pointer (SP) 20 contains a binary number whose value is equal to “the current stack top word address (ATOS)+1”. For a stack that can store 32 words, the stack pointer 20 should contain 5 bits since 25=32. A stack pointer 20 having five bits cannot exceed a number greater than 31 (‘11111’ in binary).
As illustrated in FIG. 1, five items are placed in the 32-word stack 10: A, B, C, D, and E in the order shown. With item E on top of the stack, the content of the stack pointer 20 is 5 (i.e., ‘00101’ in binary). To insert a new item, the stack storage 10 is “pushed” by storing the new item into the location indicated by the stack pointer 20 (i.e., the location at address ‘5’) and then incrementing the stack pointer 20 so as to point to the next-higher order location at address ‘6’. For removal of the top item E at address ‘4’, the stack storage 10 is “popped” by decrementing the content of the stack pointer 20 first and then retrieving the top item E from the location at address ‘4’, so that the stack pointer 20 contains ‘4’ to indicate the top location.
Typically, digital data processors are categorized in terms of the number of binary bits in the data they process, i.e., their word length. For example, an 8-bit processor to process information by 8 bits (1 byte) has an 8-bit wide stack, hence only one word (i.e., 8 bits) is able to be pushed onto the stack at a time.
A digital processor will generally be designed to have its address bit width larger than its data bit width in order to acquire an adequate amount of memory address space. For example, an 8-bit processor may have its address being 16 bits or more in size even though its data word is only 8-bit wide. In such a case, to push or pop a 16-bit address (e.g., for a subroutine call or return operation) onto or off an 8-bit stack, the 16-bit address should be first divided into two 8-bit portions, and then the two portions are pushed/popped on/off the stack in twice, which causes degradation in processor performance. Accordingly, a digital processor that provides improved performance of stack-based operations is desired.